#configure library
set_search_path		"$search path ./netiist ./lib"
set_target_library		{./lib/typical.db}
set_link_library		{*./lib/typical.db}
#read and link the design
read_verilog -netlist ./netlist/top.v
current_design_top
link
#configure DFT
set_dft_signal -type reset -port rstn -view existing_dft -active_state 0
set_dft_configuration -fix_reset enable
set_autofix_configuration -type reset -test_data rstn
set_scan_configuration -clock_mixing mix_clocks
set_scan_configuration -chain_count 1
#set_scan_configuration -mix_clocks_not_edges
set_dft_signal -type ScanClock -port clk -view existing_dft -timing {45 55}
#set_dft_signal -type ScanClock -port clkB -view existing_dft -timing {45 55}
#set_dft_signal -type reset -port rstn -view existing_dft
#preview and insert DFT
create_test_protocol
dft_drc
preview_dft
insert_dft
dft_drc
#wite out design information
report_scan_path -view existing_dft -chain all
write -format verilog -hierarchy -output netlist/top_scan.v
write_test_protocol -output generated/scan.spf
exit