module convert(
input			da	,
input			wra_n	,
input			clka	,
input			clkb	,
input			rst_n	,
output reg 		wrb		,
output reg [7:0]db
)

reg da_r;

reg [1:0] state;

reg wra_n_r;
reg sample_act, sample_act_npulse;
reg [3:0] sample_cnt;
reg [7:0] sample_data,sample_data2;

wire wra_n_nge;
assign wra_n_nge = wra_n_r & (~wra_n);

always @(posedge clka) begin
	da_r <= da;
end


always @(posedge clka or negedge rst_n) begin
	if(!rst_n) begin
		wra_n_r <= 1'b1;
	end
	else begin
		wra_n_r <= wra_n;
	end
end


always @(posedge clka or negedge rst_n) begin
	if(!rst_n) begin
		state <= 2'b01;
		sample_cnt <= 4'd0;
		sample_data <= 8'b0;
		sample_act <= 1'b0;
	end
	else begin
		case(state)
			2'b01: begin
					sample_cnt <= 4'b0;
					sample_act <= 1'b0;
					if(wra_n_nge) begin
						state <= 2'b10;
					end
			end
			2'b10:begin
				sample_data <= {sample_data[6:0] , da_r};
				if(sample_cnt >= 4'd7) begin
					sample_act <= 1'b1;
					state <= 2'b10;
				end 
				else begin
					sample_cnt <= sample_cnt +1;
				end
			end
		endcase
	end
end
always @(posedge clka or negedge rst_n) begin
	if(!rst_n) begin
		sample_act_npulse <= 1'b0;
		sample_data2 <= 8'b0;
	end
	else begin
		sample_data2 <= sample_act ? sample_data : sample_data2;
		sample_act_npulse <= sample_act_npulse ^ sample_act;
	end
end

reg [2:0]sample_act_b;

always@(posedge clkb or negedge rst_n) begin
	if(!rst_n) begin
		sample_act_b <= 3'b0;
	end
	else begin
		sample_act_b[2:0] <= {sample_act_b[0] , sample_act_npulse};
	end
end


always @(posedge clka or negedge rst_n) begin
	if(!rst_n) begin
		wrb <= 1'b0;
		db <= 8'b0;
	end
	else begin
		wrb <= sample_act_b[2] ^sample_act_b[1];
		db <= sample_act_b[1] ? sample_data2:db;
	end
end


module top_module (
input clk,
input resetn,//active-low asynchronous reset
input[2:0]r , //request, synchronized to clk posedge
output [2:0] g // grant
);


localparam  IDLE = 4'B0001,
			ACK0 = 4'B0010,
			ACK1 = 4'B0100,
			ACK2 = 4'B1000;

localparam  idle_t = 1,
			ack0_t = 2,
			ack1_t = 3,
			ack2_t = 4;
			
reg [3:0] ct_state, nt_state;
reg [2:0] grant;


wire idle_2_idle , idle_2_ack0 , idle_2_ack1 , idle_2_ack2 ;
wire ack0_2_idle , ack0_2_ack0 , ack0_2_ack1 , ack0_2_ack2 ;
wire ack1_2_idle , ack1_2_ack0 , ack1_2_ack1 , ack1_2_ack2 ;
wire ack2_2_idle , ack2_2_ack0 , ack2_2_ack1 , ack2_2_ack2 ;
wire stepinidle , stepinack0 , stepinack1, stepinack2;

assign idle_2_idle = ct_state[idle_t] && r = 3'b000;
assign idle_2_ack0 = ct_state[idle_t] && r[0] = 1'b1;
assign idle_2_ack1 = ct_state[idle_t] && r[1:0] = 2'b10;
assign idle_2_ack2 = ct_state[idle_t] && r = 3'b100;

assign ack0_2_idle = ct_state[ack0_t] && r = 3'b000;
assign ack0_2_ack0 = ct_state[ack0_t] && r[0] = 1'b1;
assign ack0_2_ack1 = ct_state[ack0_t] && r[1:0] = 2'b10;
assign ack0_2_ack2 = ct_state[ack0_t] && r = 3'b100;

assign ack1_2_idle = ct_state[ack1_t] && r = 3'b000;
assign ack1_2_ack0 = ct_state[ack1_t] && r[0] = 1'b1;
assign ack1_2_ack1 = ct_state[ack1_t] && r[1:0] = 2'b10;
assign ack1_2_ack2 = ct_state[ack1_t] && r = 3'b100;

assign ack2_2_idle = ct_state[ack2_t] && r = 3'b000;
assign ack2_2_ack0 = ct_state[ack2_t] && r[0] = 1'b1;
assign ack2_2_ack1 = ct_state[ack2_t] && r[1:0] = 2'b10;
assign ack2_2_ack2 = ct_state[ack2_t] && r = 3'b100;

assign stepinidle = idle_2_idle | ack0_2_idle |  ack1_2_idle | ack2_2_idle；
assign stepinack0 = idle_2_ack0 | ack0_2_ack0 |  ack1_2_ack0 | ack2_2_ack0
assign stepinack1 = idle_2_ack1 | ack0_2_ack1 |  ack1_2_ack1 | ack2_2_ack1
assign stepinack2 = idle_2_ack2 | ack0_2_ack2 |  ack1_2_ack2 | ack2_2_ack2


always @(posedge clk or resetn) begi
	if(!resetn) begin
		ct_state <= IDLE;
	end
	else begin
		ct_state <= nt_state;
	end
end
always@(*) begin
	nt_state = IDLE;
	case(1'b1)
		stepinidle:nt_state = IDLE ;
		stepinack0:nt_state = ACK0;
		stepinack1:nt_state = ACK1;
		stepinack2:nt_state = ACK2;
		default:nt_state = ct_state;
	endcase
end

if(r[0] == 1)
	nt_state = ACK0;
else if(r[1:0] = 2'b10)
	nt_state = ACK1;
else if(r == 3'b100)
	nt_state = ACK2;
else
	nt_state = ct_state;
	

always@(*)
	grant = ct_state[1+:3];
	
assign g = grant;

endmodule
//我是24应届-谢玉东-南航-集成电路设计-硕士 18318541191

module top(
input				clk		,
input				rst_n	,
input		[1:0]	sig_in	,
output	reg	[1:0]	db_out
);


//
localparam NUM_1MS = 20'd1000_000;

localparam IDLE = 1'b0, WAIT = 1'b1;

reg [19:0] cnt;
reg [1:0] sig_in_r;
reg ct_state , nt_state;


always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		ct_state <= IDLE;
	end
	else begin
		ct_state <= nt_state
	end
end

always @(*) begin
	case(ct_state)
		IDLE:nt_state = sig_in_r != sig_in ? WAIT : IDLE;
		WAIT:nt_state = (cnt == NUM_1MS-1'b1 || sig_in_r!= sig_in )? IDLE : WAIT; 
	endcase
end

always  @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		sig_in_r <= 2'b00;
		cnt <= 20'd0;
	end
	else begin
		case(ct_state)
			1'b0:begin
				sig_in_r <= sig_in ;
				cnt <= 20'd0;
			end
			1'b1:begin
				if(sig_in_r == sig_in) begin
					if(cnt >= NUM_1MS-1) begin
						cnt <= 20'b0;
						db_out <= sig_in_r;
					end
					else begin
						cnt <= cnt + 1'b1;
					end
				end
			end
		endcase
	end
end
endmodule