52 lines
1.0 KiB
Verilog
52 lines
1.0 KiB
Verilog
/***************************************************
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* Module Name : clk_generator
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* Engineer : Crazy Bingo
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* Target Device : EP2C8Q208C8
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* Tool versions : Quartus II 9.1SP1
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* Create Date : 2011-6-25
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* Revision : v1.0
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* Description :
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**************************************************/
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/*************************************************
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fc = 50MHz 50*10^6
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fo = fc*K/(2^32)
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K = fo*(2^32)/fc
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= fo*(2^32)/(50*10^6)
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**************************************************/
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module clk_generator
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#
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(
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parameter FREQ_WORD = 32'd8590 //1KHz
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)
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(
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input clk, //50MHz
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input rst_n, //clock reset
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output reg clk_out
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);
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//--------------------------------------
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reg [31:0] max_value;
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always@(posedge clk or negedge rst_n)
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begin
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if(!rst_n)
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max_value <= 1'b0;
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else
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max_value <= max_value + FREQ_WORD;
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end
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//--------------------------------------
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always@(posedge clk or negedge rst_n)
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begin
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if(!rst_n)
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clk_out <= 1'b0;
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else
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begin
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if(max_value < 32'h7FFF_FFFF)
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clk_out <= 1'b0;
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else
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clk_out <= 1'b1;
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end
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end
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endmodule
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