23 lines
601 B
Verilog
23 lines
601 B
Verilog
////////////////////////////////////////////////
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// Purpose: Clock_Unit for RISC_SPM
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// Author: Mike Ciletti with heavy modification
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//
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// REVISION HISTORY:
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// $Log: Clock_Unit.v,v $
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// Revision 1.1 2011/05/31 16:32:52 tumbush.tumbush
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// Check into cloud repository.
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//
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// Revision 1.1 2011/03/20 20:43:01 Greg
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// Initial check in
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//
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////////////////////////////////////////////////
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`default_nettype none
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module Clock_Unit (output reg clock);
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parameter delay = 0;
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parameter half_cycle = 10;
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initial begin
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#delay clock = 0;
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forever #half_cycle clock = ~clock;
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end
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endmodule
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