41 lines
1.4 KiB
Verilog
41 lines
1.4 KiB
Verilog
////////////////////////////////////////////////
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// Purpose: ALU for RISC_SPM
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// Author: Mike Ciletti with heavy modification
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//
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// REVISION HISTORY:
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// $Log: Alu_RISC.v,v $
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// Revision 1.1 2011/05/31 16:32:52 tumbush.tumbush
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// Check into cloud repository.
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//
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// Revision 1.1 2011/03/20 20:43:01 Greg
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// Initial check in
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//
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////////////////////////////////////////////////
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/*ALU Instruction Action
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ADD Adds the datapaths to form data_1 + data_2.
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SUB Subtracts the datapaths to form data_1 - data_2.
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AND Takes the bitwise-and of the datapaths, data_1 & data_2.
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NOT Takes the bitwise Boolean complement of data_2.
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*/
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// Note: the carries are ignored in this model.
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module Alu_RISC #(parameter word_size = 8, op_size = 4)
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(output wire alu_zero_flag, // ALU=0
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output reg [word_size-1: 0] alu_out, // Output of ALU
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input wire [word_size-1: 0] data_2, data_1, // Input data
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input wire [op_size-1: 0] opcode // Opcode to execute
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);
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`include "opcodes_include.v"
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assign alu_zero_flag = ~|alu_out;
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always @ (opcode or data_1 or data_2)
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case (opcode)
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NOP: alu_out = 0;
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ADD: alu_out = data_1 + data_2; // Reg_Y + Bus_1
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SUB: alu_out = data_2 - data_1;
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AND: alu_out = data_1 & data_2;
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NOT: alu_out = ~ data_2; // Gets data from Bus_1
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default: alu_out = 0;
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endcase
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endmodule
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