72 lines
3.5 KiB
Verilog
72 lines
3.5 KiB
Verilog
////////////////////////////////////////////////
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// Purpose: Processing unit for RISC_SPM
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// Author: Mike Ciletti with heavy modification
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//
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// REVISION HISTORY:
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// $Log: Processing_Unit.v,v $
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// Revision 1.1 2011/05/31 16:32:52 tumbush.tumbush
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// Check into cloud repository.
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//
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// Revision 1.1 2011/03/20 20:43:01 Greg
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// Initial check in
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//
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////////////////////////////////////////////////
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`default_nettype none
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module Processing_Unit #(parameter Sel1_size = 3, Sel2_size = 2, word_size = 8)
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(output wire [word_size-1: 0] Bus_1, // Output of Mux_1
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output wire [word_size-1: 0] address, // The location in memory to access
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output wire [word_size-1: 0] instruction, // Contains {opcode, src, dest} or address
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output wire Zflag, // Zero flag
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input wire [word_size-1: 0] mem_word, // Data output of memory unit
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// Load enables for registers
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input wire Load_R0, Load_R1, Load_R2, Load_R3,
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input wire Load_IR, Load_Add_R, Load_Reg_Y,
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input wire Load_PC, Inc_PC, Load_Reg_Z,
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input wire [Sel1_size-1: 0] Sel_Bus_1_Mux, // select for mux1
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input wire [Sel2_size-1: 0] Sel_Bus_2_Mux, // select for mux2
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input wire clk,
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input wire rst // Active low asynchronous reset
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);
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parameter op_size = 4; // The size of an op-code
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// Internal signals
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wire [word_size-1: 0] R0_out, R1_out, R2_out, R3_out; // Register outputs
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wire [word_size-1: 0] Y_value, alu_out, Bus_2;
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reg [word_size-1: 0] PC_count;
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wire alu_zero_flag;
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wire [op_size-1 : 0] opcode = instruction [word_size-1: word_size-op_size];
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// Instantiate any (word_size-1)-bit registers with 1 load condition
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Register_Unit R0 (.data_out(R0_out), .data_in(Bus_2), .load(Load_R0), .clk(clk), .rst(rst));
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Register_Unit R1 (.data_out(R1_out), .data_in(Bus_2), .load(Load_R1), .clk(clk), .rst(rst));
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Register_Unit R2 (.data_out(R2_out), .data_in(Bus_2), .load(Load_R2), .clk(clk), .rst(rst));
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Register_Unit R3 (.data_out(R3_out), .data_in(Bus_2), .load(Load_R3), .clk(clk), .rst(rst));
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Register_Unit Reg_Y (.data_out(Y_value), .data_in(Bus_2), .load(Load_Reg_Y), .clk(clk), .rst(rst));
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Register_Unit Reg_Add_R (.data_out(address), .data_in(Bus_2), .load(Load_Add_R), .clk(clk), .rst(rst));
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Register_Unit Reg_instr (.data_out(instruction), .data_in(Bus_2), .load(Load_IR), .clk(clk), .rst(rst));
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Register_Unit #(.word_size(1)) Reg_Zflag (.data_out(Zflag), .data_in(alu_zero_flag), .load(Load_Reg_Z), .clk(clk), .rst(rst));
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Alu_RISC ALU (.alu_zero_flag(alu_zero_flag), .alu_out(alu_out), .data_2(Bus_1), .data_1(Y_value), .opcode(opcode));
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mux5_1 Mux_1(.data_in0(R0_out), .data_in1(R1_out), .data_in2(R2_out), .data_in3(R3_out), .data_in4(PC_count),
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.sel(Sel_Bus_1_Mux), .data_out(Bus_1));
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mux3_1 Mux_2(.data_in0(alu_out), .data_in1(Bus_1), .data_in2(mem_word), .sel(Sel_Bus_2_Mux), .data_out(Bus_2));
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// Load or increment Program_Counter (signal PC_Count)
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always @ (posedge clk or negedge rst) begin
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if (rst == 0)
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PC_count <= 0;
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else if (Load_PC)
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PC_count <= Bus_2;
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else if (Inc_PC)
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PC_count <= PC_count +1;
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end
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endmodule
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