69 lines
2.8 KiB
Verilog
69 lines
2.8 KiB
Verilog
////////////////////////////////////////////////
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// Purpose: RISC_SPM top level
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// Author: Mike Ciletti with heavy modification
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//
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// REVISION HISTORY:
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// $Log: RISC_SPM.v,v $
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// Revision 1.1 2011/05/31 16:32:52 tumbush.tumbush
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// Check into cloud repository.
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//
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// Revision 1.1 2011/03/20 20:43:01 Greg
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// Initial check in
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//
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////////////////////////////////////////////////
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`default_nettype none
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module RISC_SPM #(parameter word_size = 8, parameter Sel1_size = 3, parameter Sel2_size = 2)
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(
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input wire clk,
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input wire rst, // Active low asynchronous reset
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input wire [word_size-1: 0] data_out, // Read data from memory unit - input
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output wire [word_size-1: 0] address, // Address to read/write - output
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output wire [word_size-1: 0] data_in, // Write data to memory unit - output
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output wire write // Write flag to memory unit - output
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);
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wire [Sel1_size-1: 0] Sel_Bus_1_Mux; // select for mux1
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wire [Sel2_size-1: 0] Sel_Bus_2_Mux; // select for mux2
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wire Zflag; // Zero flag
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wire [word_size-1: 0] instruction; // Contains {opcode, src, dest} or address
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wire [word_size-1: 0] Bus_1; // Output of mux_1
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wire [word_size-1: 0] mem_word; // Data output of memory unit
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// Control Nets
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wire Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC; // Load enables for registers
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wire Load_IR, Load_Add_R, Load_Reg_Y, Load_Reg_Z; // Load enables for registers
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assign mem_word = data_out;
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assign data_in = Bus_1;
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// The CPU which is a datapath plus ALU
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Processing_Unit Processor (.instruction(instruction), .Zflag(Zflag), .address(address), .Bus_1(Bus_1),
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.mem_word(mem_word), .Load_R0(Load_R0), .Load_R1(Load_R1), .Load_R2(Load_R2),
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.Load_R3(Load_R3), .Load_PC(Load_PC), .Inc_PC(Inc_PC), .Sel_Bus_1_Mux(Sel_Bus_1_Mux),
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.Load_IR(Load_IR), .Load_Add_R(Load_Add_R), .Load_Reg_Y(Load_Reg_Y),
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.Load_Reg_Z(Load_Reg_Z), .Sel_Bus_2_Mux(Sel_Bus_2_Mux), .clk(clk), .rst(rst));
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// State machine to control everything
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Control_Unit Controller (.Load_R0(Load_R0), .Load_R1(Load_R1), .Load_R2(Load_R2), .Load_R3(Load_R3),
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.Load_PC(Load_PC), .Inc_PC(Inc_PC), .Load_IR(Load_IR), .Load_Add_R(Load_Add_R),
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.Load_Reg_Y(Load_Reg_Y), .Load_Reg_Z(Load_Reg_Z), .write(write),
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.Sel_Bus_1_Mux(Sel_Bus_1_Mux), .Sel_Bus_2_Mux(Sel_Bus_2_Mux),
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.instruction(instruction), .Zflag(Zflag), .clk(clk), .rst(rst));
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/*
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// The memory unit where data and instructions are stored
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Memory_Unit SRAM (
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.data_out(mem_word),
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.data_in(Bus_1),
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.address(address),
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.clk(clk),
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.write(write) );
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*/
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endmodule
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