35 lines
1014 B
Verilog
35 lines
1014 B
Verilog
////////////////////////////////////////////////////////////////////////////////
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// Purpose: Generic 5-1 Mux for RISC_SPM design
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// Author: Mike Ciletti with heavy modification
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//
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// REVISION HISTORY:
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// $Log: mux5_1.v,v $
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// Revision 1.1 2011/05/31 16:32:52 tumbush.tumbush
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// Check into cloud repository.
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//
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// Revision 1.1 2011/03/20 20:43:01 Greg
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// Initial check in
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//
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////////////////////////////////////////////////////////////////////////////////
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`default_nettype none
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// A generic 5-1 mux.
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module mux5_1 #(parameter word_size = 8, sel_width=3)
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(input wire [word_size-1: 0] data_in0, data_in1, data_in2, data_in3, data_in4,
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input wire [sel_width-1:0] sel,
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output reg [word_size-1: 0] data_out
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);
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// Implement a 5 to 1 mux
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always @* begin
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case (sel)
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0: data_out = data_in0;
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1: data_out = data_in1;
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2: data_out = data_in2;
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3: data_out = data_in3;
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4: data_out = data_in4;
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default: data_out = 0;
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endcase
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end
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endmodule |