#--------------------------------------------------------------------
# Sources
#--------------------------------------------------------------------

# Verilog sources

bb_vsrcs = \
    $(vsrc)/plusarg_reader.v \
    $(vsrc)/ClockDivider2.v \
    $(vsrc)/ClockDivider3.v \
    $(vsrc)/AsyncResetReg.v \
    $(vsrc)/EICG_wrapper.v \

sim_vsrcs = \
    $(generated_dir)/$(long_name).v \
    $(generated_dir)/$(long_name).behav_srams.v \
    $(vsrc)/$(TB).v \
    $(vsrc)/SimDTM.v \
    $(vsrc)/SimJTAG.v \
    $(bb_vsrcs)

# C sources

sim_csrcs = \
    $(csrc)/SimDTM.cc \
    $(csrc)/SimJTAG.cc \
    $(csrc)/remote_bitbang.cc

#--------------------------------------------------------------------
# Build Verilog
#--------------------------------------------------------------------

verilog: $(sim_vsrcs)

.PHONY: verilog

#--------------------------------------------------------------------
# Build rules
#--------------------------------------------------------------------

VCS = vcs -full64

VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
	+rad +v2k +vcs+lic+wait \
	+vc+list -CC "-I$(VCS_HOME)/include" \
	-CC "-I$(RISCV)/include" \
	-CC "-std=c++11" \
	-CC "-Wl,-rpath,$(RISCV)/lib" \
	$(RISCV)/lib/libfesvr.a \
	-sverilog \
	+incdir+$(generated_dir) \
	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
	+define+PRINTF_COND=$(TB).printf_cond \
	+define+STOP_COND=!$(TB).reset \
	+define+RANDOMIZE_MEM_INIT \
	+define+RANDOMIZE_REG_INIT \
	+define+RANDOMIZE_GARBAGE_ASSIGN \
	+define+RANDOMIZE_INVALID_ASSIGN \
	+define+RANDOMIZE_DELAY=0.1 \
	+define+MODEL=$(MODEL) \
	+libext+.v \

#--------------------------------------------------------------------
# Build the simulator
#--------------------------------------------------------------------

simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG_STR)
$(simv) : $(sim_vsrcs) $(sim_csrcs)
	cd $(sim_dir) && \
	rm -rf csrc && \
	$(VCS) $(VCS_OPTS) -o $(simv) \
	-debug_pp \

simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG_STR)-debug
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
	cd $(sim_dir) && \
	rm -rf csrc && \
	$(VCS) $(VCS_OPTS) -o $(simv_debug) \
	+define+DEBUG -debug_pp \

#--------------------------------------------------------------------
# Run
#--------------------------------------------------------------------

seed = $(shell date +%s)
exec_simv = $(simv) +permissive -q +ntb_random_seed_automatic +permissive-off
exec_simv_debug = $(simv_debug) +permissive -q +ntb_random_seed_automatic +permissive-off