29 lines
1.0 KiB
Plaintext
29 lines
1.0 KiB
Plaintext
#configure library
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set_search_path "$search path ./netiist ./lib"
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set_target_library {./lib/typical.db}
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set_link_library {*./lib/typical.db}
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#read and link the design
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read_verilog -netlist ./netlist/top.v
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current_design_top
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link
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#configure DFT
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set_dft_signal -type reset -port rstn -view existing_dft -active_state 0
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set_dft_configuration -fix_reset enable
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set_autofix_configuration -type reset -test_data rstn
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set_scan_configuration -clock_mixing mix_clocks
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set_scan_configuration -chain_count 1
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#set_scan_configuration -mix_clocks_not_edges
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set_dft_signal -type ScanClock -port clk -view existing_dft -timing {45 55}
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#set_dft_signal -type ScanClock -port clkB -view existing_dft -timing {45 55}
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#set_dft_signal -type reset -port rstn -view existing_dft
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#preview and insert DFT
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create_test_protocol
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dft_drc
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preview_dft
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insert_dft
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dft_drc
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#wite out design information
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report_scan_path -view existing_dft -chain all
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write -format verilog -hierarchy -output netlist/top_scan.v
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write_test_protocol -output generated/scan.spf
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exit |